Non-contact range measurement pulse-echo radar systems for fluid level sensing in tanks and vats typically consist of a transmitter which is arranged to radiate short duration radio frequency (RF) bursts toward the surface of the product being stored in the tank or vat via a highly directional antenna. After a delay a receiver is gated at a particular point in time to receive energy which is reflected from the surface of the product. The timing of gating of the receiver is typically swept across a range of delays in a matter of milliseconds, such that a video output of the receiver can be provided as a scan like waveform. This waveform replicates occurring echoes on a real-time scale, corresponding to the physical distances represented by the echoes as the exact delay of a received echo pulse in relation to the transmitted pulse, i.e. the time of flight of the pulse, provides a measure of the distance to the reflecting object.
Highly accurate timing of the transmitted RF bursts and the gating of the receiver is necessary in order to be able to obtain high accuracy range information.
A precision digital pulse phase generator timing circuit is previously known through U.S. Pat. No. 6,300,897 B1 which relates to a radar gauge adapted to sense fluid level in a tank and including a radar gauge circuit in which radar transmission and level sampling are controlled by a transmit frequency and a sample frequency respectively. A first frequency separation between first and second frequencies is controlled by a control input. The first and second frequencies can be divided to generate the transmit and sample frequencies, separated by a second frequency separation. At least one frequency difference is evaluated and the evaluation used to generate the control input, stabilizing the first frequency difference, and to correct the gauge output.
This timing circuit previously known through FIG. 8 of U.S. Pat. No. 6,300,897 which is hereby incorporated by reference in its entirety, comprises a frequency difference circuit which receives the transmit clock frequency and the sample clock frequency and generates a frequency difference output. A polarity sensing circuit senses the polarity of the sample clock relative to the frequency difference output and generates a polarity, or sign, output. Both of these functions are suggested to be performed using low cost type 7474 clocked D flip flop circuits.
However, taking into account the timing requirements regarding setup and hold times for this kind of D flip-flop, the above separation frequency detector is not a very robust solution. If the signal at the D-input changes within the forbidden set-up and hold-time window, one of two reactions of the flip-flop can be observed:    1) The flip-flop works perfectly with no special behaviour;    2) The output of the flip-flop becomes unstable or “metastable”.If the output of a the flip-flop is “metastable”, the output voltage is higher than the low-level-limit, but lower than the high-level-limit i.e. it is in the forbidden area between digital low and high. This situation can last less than 1 ns, but could also last longer than 30 ns. Also, the state the D flip-flop goes to after being metastable is random. The resulting behavior for the prior art circuit is that, during the time frame when the phase slip between the TX and RX clock is such that the setup/hold requirements are being violated, the output signal of the D flip-flop may change state each time it is being clocked. Thus, each edge of the Delta F signal may toggle or “chatter” with the frequency of the TX-clock for a duration corresponding to the sweep/phase slip time when the setup/hold time are being violated.
Another issue is that the TX and RX clock will always have some degree of phase noise. If the phase slip l separation frequency is slow enough the output may toggle or “chatter” simply due to the phase noise of the clock signals. However, the D flip-flop will only toggle for sure if the maximum differential phase noise between the two clock signals is greater than the sum of the setup and hold time for the flip-flop.